1. Field of the Invention
This invention relates to an image compression and decompression apparatus which compresses and decompresses an image, and more particularly to an image compression and decompression apparatus which compresses and decompresses an image in a computer system.
2. Description of the Related Art
In recent years, systems wherein video images are digitized to obtain image data and the image data are processed by various processes including transfer or display of data have been and are used in practical use.
However, since a large amount of data are obtained by digitization of video images, various problems are encountered in that much time is required for transfer of data, that a large scale is required for a storage medium or that a storage medium is occupied at a high rate by the data. Accordingly, in an image data processing system for a transfer system or a storage system, it is required to efficiently compress data after digitization to reduce the amount of data to be transferred or stored and decompress the thus compressed data so as to allow reproduction or processing of the data.
One of such systems as described above is disclosed in Japanese Patent Laid-Open Application No. Showa 62-195987. In particular, the prior art document discloses an image coding and decoding apparatus wherein a buffer for data in units of a video frame is interposed between a pre-processing section and a coding section and between the coding section and a video outputting section of a coder and the coding processing rate is decreased in response to a transmission rate while time division processing is employed to achieve reduction of the scale of the apparatus and improvement in coding efficiency. The coding section, that is, an image compression circuit, of the image coding and decoding apparatus disclosed in the prior art document is shown in FIG. 11, and a decoding section, that is, an image decompression section, disclosed in the prior art document is shown in FIG. 12.
Referring first to FIG. 11, the image compression circuit shown includes an analog to digital (A/D) converter 71, a time integration circuit 72, a switch 73, first and second pre-frame memories 74 and 75, a selector 76, a pre-frame memory controller 77, an interframe coding circuit 78, a frame memory 79, a switch 80, first and second transmission buffers 81 and 82, and a selector 83. A pre-frame memory of the double buffer structure is formed from the switch 73, first and second pre-frame memories 74 and 75, and selector 76. Meanwhile, a transmission buffer of the double buffer structure is formed from the switch 80, first and second transmission buffers 81 and 82, and selector 83.
Operation of the components of the image compression circuit will be described below. Each of the first and second pre-frame memories 74 and 75 has a storage capacity for data for at least one image frame. The analog to digital converter 71 digitizes an input video signal and outputs a digital video signal. The time integration circuit 72 integrates the digital video signal with respect to time in units of an image frame. The switch 73 switchably writes the image frame integrated with respect to time by the time integration circuit 72 into the first or second frame memory 74 or 75. The selector 76 reads data from the first or second pre-frame memory 74 or 75 with which writing of data is not proceeding. The pre-frame memory controller 77 controls writing and reading of data into and from the first and second pre-frame memories 74 and 75. The frame memory 79 has a storage capacity for data for at least one image frame. The interframe coding circuit 78 receives a signal read out from the first or second frame memory 74 or 75 as an input signal thereto, locally decodes picture elements which have been decoded already, stores the locally decoded picture elements into the frame memory 79, forms an interframe predictive signal, and performs interframe coding in units of a predetermined amount of picture elements in such a method that the picture elements can be coded and decoded sequentially. The first and second transmission buffers 81 and 82 can store coded information obtained from the interframe coding circuit 78. The switch 80 switchably writes sequentially coded information into the first or second transmission buffer 81 or 82. The selector 83 reads data from the first or second transmission buffer 81 or 82 with which wiring of data is not proceeding. The signal selected by the selector 83 is transmitted as a transmission signal of the image compression circuit.
In this manner, the image compression circuit of FIG. 11 can decrease drops of data in the direction of the time base by the arrangement of the two pre-frame memories 74 and 75 and the two transmission buffers 81 and 82.
Meanwhile, the image decompression circuit shown in FIG. 12 includes a reception buffer 91, an interframe decoding circuit 92, a frame memory 93, a switch 94, first to third post-frame memories 95, 96 and 97, a selector 98, and a digital to analog (D/A) converter 99. A post-frame memory of the triple buffer structure is constructed from the switch 94, first to third post-frame memories 95, 96 and 97, and selector 98.
Subsequently, operation of the image decompression circuit shown in FIG. 12 will be described. The reception buffer 91 can sequentially store and read out a received coded signal (transmission signal). The frame memory 93 has a storage capacity for data for at least one image frame. The interframe decoding circuit 92 receives a signal read out from the reception buffer 91 as an input signal thereto, stores picture elements which have been decoded already into the frame memory 93, forms an interframe predictive signal, and effects sequential interframe decoding in accordance with the coding method which has been employed by the interframe coding circuit 78 shown in FIG. 11. Each of the first to third post-frame memories 95 to 97 has a storage capacity for data for at least one image frame. The switch 94 switchably writes a decoded signal outputted from the interframe decoding circuit 92 into the first, second or third post-frame memory 95, 96 or 97. The selector 98 selectively reads out a decoded image frame stored in the first, second or third post-frame memory 95, 96 or 97, with which writing is not proceeding, in synchronism with a frame synchronizing signal of an image outputting system. The digital to analog converter 99 converts a signal selected by the selector 98 into a decoded video signal.
The image decompression circuit of FIG. 12 can reduce drops of data in the direction of the time base by the arrangement of the three post-frame memories 95 to 97 in this manner.
The image compression and decompression apparatus, however, is disadvantageous in that it is large in scale and high in cost since it includes, as seen from FIGS. 11 and 12, the frame memories 74, 75, 79, 93, 95, 96 and 97 for seven frames.
Several other systems of the type described above are also known including an image processing system disclosed in Japanese Patent Laid-Open Application No. Showa 61-176264, wherein, when an abnormal condition of a decompression operation of decompression means is detected by detection means, a normal decompressed image signal stored in storage means is supplied to output means in place of the decompressed image in which the abnormal condition has been detected so that an image output free from a disorder can be obtained. The image processing system is directed to a countermeasure against an error in decompression. Meanwhile, Japanese Patent Laid-Open Application No. Showa 61-176253 discloses an image processing system which is directed to elimination of a density difference between a compressed binary image and an original image, in the image processing system, the density analysis degrees of image signals from output means and storage means to be supplied to formation means upon image formation are made coincide with each other so that an image can be formed normally in an equal density. Further, Japanese Patent Laid-Open Application No. Showa 56-138377 discloses a video signal multiple carrying system which is directed to a transmission system for an analog video signal. In the video signal multiple carrying system, individual video signals are compressed by time base compression at rates which increase in inverse proportion to frequency bands of them to uniform the video bands of them and then the video signals of the uniform video band are composed by time division composition and transmitted in order to decrease the number of required frequency bands.